The present invention relates to the area of serial digital data transmissions. It relates more particularly to a synchronous bus and its master/slave transmission protocol between a main processing unit (master) and a peripheral unit (slave).
An example of such a bus, used in different categories of equipment, is the so-called I.sup.2 C bus described in European patent 0 051 332. A certain number of clock cycles are required for the microprocessor or microcontroller constituting the main processing unit to retrieve one byte of data (58 clock cycles in the case of the circuit marketed by the PHILIPS company with the reference number PCD 3316 which employs such a bus).
An object of the present invention is to propose a new synchronous serial bus protocol enabling faster access to certain data in the peripheral unit.